ESP1104
Introduction to Electronic Systems Part II: Digital Systems
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Office: E5-3-9
Office hour: Tuesday: 5-6pm Useful web site:
http://www.allaboutcircuits.com/vol_4/index.html
Lecture 7: Basic Digital Logic Circuits
1. State the advantages of digital technology compared to analog technology.
2. Convert numbers between decimal, binary, and other forms. 3. Understand the binary arithmetic operations used in computers and other digital systems.
4. Understand the basic logic gates (AND, NOT, and OR) and the principles of building them based on diodes and transistors.
Basic Concepts of Digital Signal
Analog signal: each amplitude in a continuous range has a unique significance.
Digital signal: only a few restricted ranges of amplitude are allowed. For example, binary signals: Logic values 0 or 1.
So the only things we deal with are 0 and 1, as simple as that! Then computers or other digital circuits can be used to process the information.
Advantages of the Digital Approach:
• Provided that the noise amplitude is not too large, the logic values represented by a digital signal can still be determined after noise is added.
• With modern IC technology, it is possible to manufacture exceedingly complex digital circuits economically.
A logic circuit, such as transistor-transistor logic (TTL), only needs to produce a voltage somewhere in the correct range. Thus, component values in digital circuits do not need to be as precise as in analog circuits.
Positive versus Negative Logic
Positive logic: higher amplitude in a binary system represents 1, and lower amplitude range represents 0.
Negative logic: higher amplitude in a binary system represents 0, and lower amplitude range represents 1.
Unless stated otherwise, we assume positive logic throughout our course.
Digital Words
A single binary digit, called a bit. To represent more information, we use groups of logic variables called digital words. A byte is a word consisting of eight bits, and a nibble is a four-bit word.
In parallel transmission, an n-bit word is transferred on n wires, one wire for each bit, plus a common or ground wire. In serial transmission, the successive bits of the word are transferred one after the other with a single pair of wires.
Numerical Data in Binary Form
Binary Numbers
Digital words can represent numerical data. Decimal number:
1 0
1 2
10
7 10 4 10 3 10 2 10
2
.
743 = × + × + × + ×
−Binary number:
10 1
0 1
2 3
2
1 2 1 2 0 2 1 2 1 2 13 . 5
1
.
1101 = × + × + × + × + ×
−=
3-bit word:
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
Conversion of Decimal to Binary Form
To convert a decimal integer to binary, we repeatedly divid by 2 till the quotient is 0. Then, the remainders read in reverse order give the binary form of number.
To convert decimal fractions to binary fractions, we repeatedly multiply the fraction part by 2, and retain the whole parts of the results as the successive bits of the binary fraction.
Binary Arithmetic
Hexadecimal and Octal Numbers
317.28=011 001 111. 0102
F3A.216=1111 0011 1010. 00102
Binary-Coded Decimal (BCD) Format
Decimal numbers are represented in binary form simply by writing the four-bit equivalent or each digit.
93.2=1001 0011. 0010BCD
197=0001 1001 0111BCD
Code 1010, 1011, 1100, 1110, and 1111 do not occur in BCD.
Gray code
A better scheme for coding the positions is to use gray code. Each code word differs in only one bit from its neighboring code words. Thus, errors in position indications are avoided during transitions.
Complement Arithmetic
The one’s complement of a binary number is obtained by replacing 1s by 0s, and vice versa.
01001101
10110010 (one’s complement)
The two’s complement of a binary number is obtained by adding 1 to the one’s complement, neglecting the carry (if any) out of the most significant bit.
(N-bit binary number) + (one’s complement)=N-bit “1”s (N-bit binary number) + (two’s complement)
=N-bit “0”s (neglecting the carry out of the most significant bit)
= 0
Therefore,
two’s complement = -(N-bit binary number)
Complements are useful for representing negative numbers and performing subtraction in computers. And the use of complement arithmetic simplifies the design of digital computers.
Most common is the signed two’s-complement representation, in which the first bit is taken as the sign bit.
Positive number: the first bit is 0
Negative Number: the first bit is 1, represented as the two’s complement of the corresponding positive number.
Subtraction Using Two’s-Complement Arithmetic:
Overflow and Underflow:
In performing arithmetic using two’s-complement arithmetic, we must be aware of the possibility of overflow in which the result exceeds the maximum value that can be represented by the word length in use. Similarly, underflow occurs if the results are less than the minimum.
9710=01100001 6310=00111111
9710 + 6310=01100001 + 00111111=10100000= -9610 (???)
-9710=10011111 -6310=11000001
(-9710) +( -6310)=10011111 + 11000001 = 01100000= 9610 (???)
If the two numbers to be added have the same sign and the results has the opposite sign, underflow or overflow occurs.
If the two numbers to be added have the different signs, the results will NOT underflow or overflow.
Basic Logic Gates
AND Gate (Logical Multiplication)
One way to specify a combinatorial logic system is to list all the possible combinations of the input variables and the corresponding output values. Such a listing is called truth table.
A
AA =
A
A 1 =
0
0 =
A
BA
AB =
( ) ( ) BC AB C ABC
A = =
NOT Gate (Logic Inverter)
= 0
A
A
A
A =
OR Gate (Logic Addition)
A
A + 0 =
1
1 =
+
A
= 1
+ A
A
( A A + + A B = ) + A C = A + ( B + C ) = A + B + C
( B C ) AB AC
A + = +
Boolean Algebra:
Manipulations of logic variables by the AND, OR, and NOT operations, named for mathematician George Boole.
One way to prove a Boolean algebra identity is to produce a truth table that lists all the possible combinations of the variables and to show that both sides of the expression yield the same results.
Prove the associative law for the OR operation: (A+B)+C=A+(B+C)
Diode Logic
Diode Logic makes use of the fact that diode will conduct an electrical current in one direction, but not in the other. In this manner, the diode acts as an electronic switch.
The following figure shows a basic Diode Logic OR gate. We’ll assume that a logic 1 is represented by +5 volts, and a logic 0 is represented by ground, or zero volts. In this figure, if both inputs are left unconnected or are both at logic 0, output Z will also be held at zero volts by the resistor, and will thus be a logic 0 as well. However, if either input is raised to +5 volts, its diode will become forward biased and will therefore conduct. This in turn will force the output up to logic 1. If both inputs are logic 1, the output will still be logic 1. Hence, this gate correctly performs a logical OR function.
The following figure shows the equivalent AND gate. We use the same logic levels, but the diodes are reversed and the resistor is set to pull the output voltage up to a logic 1 state. For this example, +V = +5 volts, although other voltages can just as easily be used. Now, if both inputs are unconnected or if they are both at logic 1, output Z will be at logic 1. If either input is grounded (logic 0), that diode will conduct and will pull the output down to logic 0 as well. Both inputs must be logic 1 in
In both of these gates, we have made the assumption that the diodes do not introduce any errors or losses into the circuit. This is not really the case; a silicon diode will experience a forward voltage drop of about 0.65v to 0.7v while conducting. But we can get around this very nicely by specifying that any voltage above +3.5 volts shall be logic 1, and any voltage below +1.5 volts shall be logic 0. It is illegal in this system for an output voltage to be between +1.5 and +3.5 volts; this is the undefined voltage region.
Individual gates like the two above can be used to advantage in specific circumstances. However, when DL gates are cascaded, as shown in the following figure, some additional problems occur. Here, we have two AND gates, whose outputs are connected to the inputs of an OR gate. Very simple and apparently reasonable.
But wait a minute! If we pull the inputs down to logic 0, sure enough the output will be held at logic 0. However, if both inputs of either AND gate are at +5 volts, what will the output voltage be? That diode in the OR gate will immediately be forward biased, and current will flow through the AND gate resistor, through the diode, and through the OR gate resistor.
If we assume that all resistors are of equal value (typically, they are), they will act as a voltage divider and equally share the +5 volt supply voltage. The OR gate diode will insert its small loss into the system, and the output voltage will be about 2.1 to 2.2 volts. If both AND gates have logic 1 inputs, the output voltage can rise to about 2.8 to 2.9 volts. Clearly, this is in the
"forbidden zone," which is not supposed to be permitted.
a reverse-biased diode somewhere blocking the input signals and preventing the circuit from operating correctly. This is why Diode Logic is used only for single gates, and only in specific circumstances.
Resistor-Transistor Logic
Consider the most basic transistor circuit, such as the one shown in the following. We will only be applying one of two voltages to the input I: 0 volts (logic 0) or +V volts (logic 1). The exact voltage used as +V depends on the circuit design parameters; in RTL integrated circuits, the usual voltage is +3.6v. We’ll assume an ordinary NPN transistor here, with a reasonable DC current gain, an emitter-base forward voltage of 0.65 volt, and a collector-emitter saturation voltage no higher than 0.3 volt. In standard RTL ICs, the base resistor is 470 and the collector resistor is 640 .
When the input voltage is zero volts (actually, anything under 0.5 volt), there is no forward bias to the emitter-base junction, and the transistor does not conduct. Therefore no current flows through the collector resistor, and the output voltage is +V volts. Hence, a logic 0 input results in a logic 1 output.
When the input voltage is +V volts, the transistor's emitter- base junction will clearly be forward biased. For those who like the mathematics, we'll assume a similar output circuit connected
2.95v / 1110 = 0.0026576577 A = 2.66 mA.
RTL is a relatively old technology, and the transistors used in RTL ICs have a DC forward current gain of around 30. If we assume a current gain of 30, 2.66 mA base current will support a maximum of 79.8 mA collector current. However, if we drop all but 0.3 volts across the 640 collector resistor, it will carry 3.3/640 = 5.1 mA. Therefore this transistor is indeed fully saturated; it is turned on as hard as it can be.
With a logic 1 input, then, this circuit produces a logic 0 output. We have already seen that a logic 0 input will produce a logic 1 output. Hence, this is a basic inverter circuit.
As we can see from the above calculations, the amount of current provided to the base of the transistor is far more than is necessary to drive the transistor into saturation. Therefore, we have the possibility of using one output to drive multiple inputs of other gates, and of having gates with multiple input resistors. Such a circuit is shown in following.
In this circuit, we have four input resistors. Raising any one input to +3.6 volts will be sufficient to turn the transistor on, and applying additional logic 1 (+3.6 volt) inputs will not really have any appreciable effect on the output voltage. Remember that the forward bias voltage on the transistor's base will not exceed 0.65 volt, so the current through a grounded input resistor will not exceed 0.65v/470 = 1.383 mA. This does provide us with a practical limit on the number of allowable
input resistors to a single transistor, but doesn't cause any serious problems within that limit.
The RTL gate shown above will work, but has a problem due to possible signal interactions through the multiple input resistors. A better way to implement the NOR function is shown to in following.
Here, each transistor has only one input resistor, so there is no interaction between inputs. The NOR function is performed at the common collector connection of all transistors, which share a single collector load resistor.
This is in fact the pattern for all standard RTL ICs. The very commonly-used µL914 is a dual two-input NOR gate, where each gate is a two-transistor version of the circuit to the left. It is rated to draw 12 mA of current from the 3.6V power supply when both outputs are at logic 0. This corresponds quite well with the calculations we have already made.
Standard fan-out for RTL gates is rated at 16. However, the fan-in for a standard RTL gate input is 3. Thus, a gate can produce 16 units of drive current from the output, but requires 3
and typically have a fan-in of 1 and a fan-out of 2 or 3. They also have reduced frequency response, so they cannot operate as rapidly as the standard gates. To get greater output drive capabilities, buffers are used. These are typically inverters which have been designed with a fan-out of 80. They also have a fan-in requirement of 6, since they use pairs of input transistors to get increased drive.
We can get a NAND function in either of two ways. We can simply invert the inputs to the NOR/OR gate, thus turning it into an AND/NAND gate, or we can use the circuit shown in the following.
In this circuit, each transistor has its own separate input resistor, so each is controlled by a different input signal. However, the only way the output can be pulled down to logic 0 is if both transistors are turned on by logic 1 inputs. If either input is a logic 0 that transistor cannot conduct, so there is no current through either one. The output is then a logic 1. This is the behavior of a NAND gate. Of course, an inverter can also be included to provide an AND output at the same time.
The problem with this NAND circuit stems from the fact that transistors are not ideal devices. Remember that 0.3 volt collector saturation voltage? Ideally it should be zero. Since it
isn't, we need to look at what happens when we "stack" transistors this way. With two, the combined collector saturation voltage is 0.6 volt -- only slightly less than the 0.65 volt base voltage that will turn a transistor on.
If we stack three transistors for a 3-input NAND gate, the combined collector saturation voltage is 0.9 volt. This is too high; it will promote conduction in the next transistor no matter what. In addition, the load presented by the upper transistor to the gate that drives it will be different from the load presented by the lower transistor. This kind of unevenness can cause some odd problems to appear, especially as the frequency of operation increases. Because of these problems, this approach is not used in standard RTL ICs.
CMOS Logic
CMOS logic is based on the use of complementary MOS transistors to perform logic functions with almost no current required. This makes these gates very useful in battery-powered applications. The fact that they will work with supply voltages as low as 3 volts and as high as 15 volts is also very helpful.
CMOS gates are all based on the fundamental inverter circuit shown in the following. Note that both of the transistors are enhancement-mode MOSFETs; one N-channel with its source grounded, and one P-channel with its source connected to +V. Their gates are connected together to form the input, and their drains are connected together to form the output.
The two MOSFETs are designed to have matching characteristics. Thus, they are complementary to each other. When off, their resistance is effectively infinite; when on, their channel resistance is about 200 . Since the gate is essentially an open circuit it draws no current, and the output voltage will be equal to either ground or to the power supply voltage, depending on which transistor is conducting.
When input A is grounded (logic 0), the N-channel MOSFET is unbiased, and therefore has no channel enhanced within itself. It is an open circuit, and therefore leaves the output line disconnected from ground. At the same time, the P-channel
MOSFET is forward biased, so it has a channel enhanced within itself. This channel has a resistance of about 200 , connecting the output line to the +V supply. This pulls the output up to +V (logic 1).
When input A is at +V (logic 1), the P-channel MOSFET is off and the N-channel MOSFET is on, thus pulling the output down to ground (logic 0). Thus, this circuit correctly performs logic inversion, and at the same time provides active pull-up and pull-down, according to the output state.
This concept can be expanded into NOR and NAND structures by combining inverters in a partially series, partially parallel structure. The circuit in the following is a practical example of a CMOS 2-input NOR gate.
In this circuit, if both inputs are low, both P-channel MOSFETs will be turned on, thus providing a connection to +V. Both N-channel MOSFETs will be off, so there will be no
The structure can be inverted, as shown in the following. Here we have a two-input NAND gate, where a logic 0 at either input will force the output to logic 1, but it takes both inputs at logic 1 to allow the output to go to logic 0.
This structure is less limited than the bipolar equivalent would be, but there are still some practical limits. One of these is the combined resistance of the MOSFETs in series. As a result, CMOS gates with more than four inputs are built as cascading structures rather than single structures. However, the logic is still valid.
